/ VerilogA for pll, fredivi, veriloga
// Author: Fuding Ge
`include "constants.h"
`include "discipline.h"
module frediv (out, in);
input in; output out; electrical in, out;
parameter real vlo=0, vhi=3;
parameter integer ratio=25 from [2:inf);
parameter integer dir=1 from[-1:1] exclude 0;
parameter real tt=1n from (0:inf);
parameter real td=10p from (0:inf);
parameter real jitter=0 from [0:td/5);
parameter real ttol=1p from (0:td/5);
integer count, n, seed;
real dt;
analog begin
@(initial_step) seed=-311;
@(cross(V(in)-(vhi+vlo)/2, dir, ttol)) begin
count=count+1;
if (count >= ratio)
count=0;
n=(2*count >= ratio);
dt=0.707*jitter*$dist_normal(seed,0,1);
end
V(out) <+ transition(n? vhi:vlo, td+dt,tt);
end
endmodule
               (
geocities.com/fudinggepll)